“LogN+1” and “LogN” Cache Models, A Binary Tree Based Cache System for Multi-core Processors

For general purpose multi-core computing, memory design especially cache implementation is one of the important issues. Program execution is often limited by the memory bottleneck, not processor availability and speed. Multi-core processors can exacerbate the problem unless care is taken to conserve memory bandwidth and avoid memory contention. Also, the absence of explicit commands to move data between core and cache in general programming languages makes it more difficult to place and trace the data in cache optimally. These foreseen problems are forcing the hardware designers to define a proper cache system for multi-core processors that work optimally and effectively for all types of data structures. During the course of our PhD project we are able to propose a novel multi-level cache system for multi-core processors. It has presented in our papers [3, 4] which also enabled us to earn a US patent approval. In this chapter we have presented this novel cache system and its two possible implementations (models) LogN+1 and LogN. This cache system is based on binary tree data structure. To begin with, the present 3-level cache system and related improvements for multi-core processors are discussed. Next, the new proposed cache system with its two models LogN+1 and LogN are discussed. In the end, the performance of these two proposed cache models is analysed and compared with the present 3-level cache system using the probabilistic mathematical model. These models are further analysed and evaluated using queuing model and simulation which are discussed in the subsequent chapters 4 and 5 respectively.